TPS-VP1902-ID+ High Performance FPGA Platform

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System Application

• Gigabit Ethernet
  • Xilinx Vivado Tool Downlo ad FPGA Design File. (Include ILA)
  • TPS m-View management system for Self-Test and FPGA Peripheral Setting.
• USB2.0
  • Xilinx Vivado Tool Download FPGA Design File. (Include ILA)
  • TPS m-View management system for Self-Test and FPGA Peripheral Setting.

Features

Large Capacity & Scalable

• Up to 18,507K System logic cells and 858Mb of internal memory(Block Ram and Ultra Ram).
• Small form factor. (412 × 312 × 131 mm, Includes chassis)
• On-board 2*DDR4 SO-DIMM socket supports up to 32GB memory, 2667Mbps (Use Xilinx MIG IP).
• On-board 2*LPDDR4 component supports up to 2GB memory, 3900Mbps (Total 4GB, Use Xilinx NoC IP).
• Multiple Logic Modules can be conveniently connected together to expand capacity by interconnection modules.

Flexible & Powerful I/Os

• 924 XPIO pins through 6 high-speed connectors(CON1~ CON6). XPIO voltage can be adjusted to 1V,1.2V, 1.35V or 1.5Vthrough runtime software in GUI or change Configuration file in SD Card.
• 64 Gigabit transceivers and 44 HD I/O pins through 4 high-speed connector(CON7~CON10) can run up to 16Gbps(GTYP), HD I/O voltage can be adjusted to1.8V, 2.5V or 3.3V through runtime software in GUI or change Configuration file in SD Card.
• Total I/O Pins = 924 XPIOs + 44 HD I/Os + 64 GTYP IOs + 274 XPIOs for 2* On-board DDR4 SO-DIMM socket + 16 GTM IOs and 14 XPIOs for 2*QSFP-DD Connector + 2*LPDDR4 component.
• XPIO Voltage Adjustment range: 1V ~ 1.8V, resolution: 50mV
• HD I/O Voltage Adjustment range: 1.8V ~ 3.3V, resolution: 50mV (1.15~3V), resolution:100mV(3.1~3.3V)

Clock Sources Management

• 8 Global clocks to be selected from 
  • 2 programmable clock generator for 8 global clocks. (10-650MHz, 8 different frequency channels)
  • Clock frequency can be adjusted through runtime software in GUI or change Configuration file in SD Card.
• 4 GTYP/Ref clocks to be selected from 
  • 1 programmable clock generatorfor 4 GTYP reference clocks. (10-650MHz, 4 different frequency channels)
  • Clock frequency can be adjusted through runtime software in GUI or change Configuration file in SD Card.
• 4 GTM/Ref clocks to be selected from 
  • 1 programmable clock generatorfor 4 GTM reference clocks. 
  • 4 different frequency channels , 12 frequencies can be selected. (10MHz/25MHz/33.33MHz/50MHz/100MHz/125MHz/156.25MHz/166.67MHz/250MHz/312.5MHz/500MHz/625MHz)
  • Clock frequency can be adjusted through runtime software in GUI or change Configuration file in SD Card.

Power Management

• 7 Group IO Connectors Power Adjustable. (6 XPIO Connectors + HD IOs on 4 GTYP Connectors for a group)
• Every XPIO Connector provide adjusted voltage power supply. (Total Current Driver Capacity 20A)
• HD I/Os on 4*GTYP Connectors for a group provide adjusted voltage power supply. (Total Current Driver Capacity 20A)
• Independent provide VCC5V power supply for 10 IO Connectors shared. (Total Current Driver Capacity 20A)

High Performance

• Up to 250W of power for an FPGA.
• On-board support of high-speed DDR4 memory(2667Mbps，Use Xilinx MIG IP).
• On-board support of high-speed LPDDR4 memory(4GB/3900Mbps，Use Xilinx NoC IP).
• Equal trace length for I/Os from same I/O connector.
• Speed Grade (External Loopback, through the Loopback Card/Module)
  • GTYP Transceiver
    • 16 Gbps.
  • QSFP D-D Connector
    • 56 Gbps (PAM4).

High Reliability

• Screw-lock design to I/O connectors.
• Self-Tests – Isolate design issues from board issues conveniently with a software GUI.(TPS m-View management system)
• Monitoring of on-board voltage, current and temperature with a software GUI.(TPS m-View management system)
• Automatic shut-down upon detection of over-current, over-voltage or over-temperature.

Ease-of-Use

• Auto diagnosis of TPSIC detect loopback card.
• Multiple FPGA configuration options through Ethernet port, USB port, JTAG , micro SD card and QSPI Flash.
• Support VP1902 FPGA 4 input/4 output GPIO for GUI Control.
• Virtual SWs for simple tasks such as changing a setting or indicating a condition .