TPS-VU19P-I+ High Performance FPGA Platform

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• The TPS-VU19P-I+ High Performance FPGA Platform is the small form-factor, all-purpose, stand-alone system based on Xilinx’s Virtex UltraScale+ XCVU19P FPGA(XCVU19P-2FSVA3824E).
• The system has 1174 general purpose I/Os and 12 GTY transceivers on 8 high-speed connectors.
• Both HP I/O voltage can be adjustedto 1V, 1.2V, 1.35V, 1.5V, and 1.8V(Adjustment range: 0.95V ~ 1.85V, resolution: 50mV), it can through runtime software in GUI or change Configuration file in SD Card with 12 statusLEDs on-board to indicate I/O voltage.
• Both HD I/O voltage can be adjusted to 1.2V, 1.35V, 1.5V,1.8V, 2.5V and 3.3V(Adjustment range: 1.15V ~ 3V, resolution: 50mV, 3V ~ 3.4V, resolution: 100mV), it can through runtime software in GUI or change Configuration file in SD Card with 4 status LEDs on-board to indicate I/O voltage.
• Utilizing TPS m-View management system technology, users can review Peripheral Setting through USB2.0.
• JTAG Interface for FPGA configuration.

Large Capacity & Scalable

• Up to 8,938K System logic cells and 165.9Mb of internal memory(Block Ram and Ultra Ram).
• Small form factor. (360 × 250 mm)

Flexible & Powerful I/Os

• 1078 HP I/O pins through 4 high-speed connectors(J1~J7). HP I/O voltage can be adjusted to 1V,1.2V, 1.35V, 1.5V or 1.8V through runtime software in GUI or change Configuration file in SD Card with 3 status LEDs on-board to indicate I/O voltage.
• 12 Gigabit transceivers and 96 HD I/O pins through 1 high-speed connector(J8) can run up to 12.5Gbps(GTY), HD I/O voltage can be adjusted to1.2V, 1.35V, 1.5V, 1.8V, 2.5V or 3.3V through runtime software in GUI or change Configuration file in SD Card with 4 status LEDs on-board to indicate I/O voltage.
• Total I/O Pins = 1078 HP I/Os + 96 HD I/Os + 12 GTY.
• HP I/O Voltage Adjustment range: 0.95V ~ 1.85V, resolution: 50mV
• HD I/O Voltage Adjustment range: 1.15V ~ 3.4V, resolution: 50mV (1.15~3V), resolution:100mV(3.1~3.4V)

Clock Sources Management

• 7 global clocks to be selected from 
  • 2 programmable clock generator for 7 global clocks. (10-650MHz, 7 different frequencies)
  •  2 OSC sources for 2 programmable clock generator.
  • Clock frequency can be adjusted through runtime software in GUI or change Configuration file in SD Card.
• 1 GTY/Ref clocks to be selected from 
  •  1 programmable clock generator for 1 GTY reference clocks. (10-650MHz)
  • Clock frequency can be adjusted through runtime software in GUI or change Configuration file in SD Card.

Power Management

• 8 Group IO Connectors Power Adjustable. (7 HP IO Connectors + 1 HD IO Connector)
• Every HP Connector provide adjusted voltage power supply. (Total Current Driver Capacity 20A)
• 1 HD Connectors for a group provide adjusted voltage power supply. (Total Current Driver Capacity 20A)
• Independent provide VCC5V power supply for 8 IO Connectors shared. (Total Current Driver Capacity 20A)

High Performance

• Up to 200W of power for an FPGA.
• Equal trace length for I/Os from same I/O connector.
• Speed Grade (External Loopback, through the Loopback Card)
  • LVDS Component Mode Performance
    • HP IO Connectors: LVDS TX/RX DDR 1200 Mbps.
    • GTY Transceiver: 12.5 Gbps.

High Reliability

• Screw-lock design to I/O connectors.
• Self-Tests – Isolate design issues from board issues conveniently with a software GUI.(TPS m-View management system)
• Monitoring of on-board voltage, current and temperature with a software GUI.(TPS m-View management system)
• Automatic shut-down upon detection of over-current, over-voltage or over-temperature.

Ease-of-Use

• Auto diagnosis of TPSIC detect loopback card.
• FPGA configuration through the JTAG.
• Support VU19P FPGA 4 input/4 output GPIO for GUI Control.
• Virtual SWs for simple tasks such as changing a setting or indicating a condition .